{"product_id":"logic-design-and-verification-using-systemverilog-revised-paperback","title":"Logic Design and Verification Using SystemVerilog (Revised) - Paperback","description":"\u003cp\u003eby \u003cb\u003eDonald Thomas\u003c\/b\u003e (Author)\u003c\/p\u003e\u003cp\u003eSystemVerilog is a Hardware Description Language that enables designers to work at the higher levels of logic design abstractions that match the increased complexity of current day integrated circuit and field-programmable gate array (FPGA) designs. The majority of the book assumes a basic background in logic design and software programming concepts. It is directed at: -students currently in an introductory logic design course that also teaches SystemVerilog, -designers who want to update their skills from Verilog or VHDL, and -students in VLSI design and advanced logic design courses that include verification as well as design topics. The book starts with a tutorial introduction on hardware description languages and simulation. It proceeds to the register-transfer design topics of combinational and finite state machine (FSM) design - these mirror the topics of introductory logic design courses. The book covers the design of FSM-datapath designs and their interfaces, including SystemVerilog interfaces. Then it covers the more advanced topics of writing testbenches including using assertions and functional coverage. A comprehensive index provides easy access to the book's topics.The goal of the book is to introduce the broad spectrum of features in the language in a way that complements introductory and advanced logic design and verification courses, and then provides a basis for further learning.Solutions to problems at the end of chapters, and text copies of the SystemVerilog examples are available from the author as described in the Preface.\u003c\/p\u003e\u003ch3\u003eAuthor Biography\u003c\/h3\u003e\u003cp\u003eDonald Thomas is Professor Emeritus of Electrical and Computer Engineering at Carnegie Mellon University where he has taught logic design, RT-level design, design languages (Verilog and SystemVerilog), verification, and computer-aided design algorithms for the design of integrated circuits and systems.\u003c\/p\u003e\u003cdiv\u003e\n\u003cstrong\u003eNumber of Pages:\u003c\/strong\u003e 336\u003c\/div\u003e\u003cdiv\u003e\n\u003cstrong\u003eDimensions:\u003c\/strong\u003e 0.7 x 9.69 x 7.44 IN\u003c\/div\u003e\u003cdiv\u003e\n\u003cstrong\u003ePublication Date:\u003c\/strong\u003e March 01, 2016\u003c\/div\u003e","brand":"Books by splitShops","offers":[{"title":"Default Title","offer_id":42743214112831,"sku":"9781523364022","price":113.32,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0105\/8226\/1823\/files\/7b0ebfa58bedbbda3b91048f83a49658.webp?v=1765165244","url":"https:\/\/dhlswag.com\/products\/logic-design-and-verification-using-systemverilog-revised-paperback","provider":"BBB","version":"1.0","type":"link"}